Non Contiguous MCQ Quiz - Objective Question with Answer for Non Contiguous - Download Free PDF

Concept:

Dirty bit: Dirty bit is associated with a block of cache memory and it is used to show the page that is modified after being loaded into cache memory.

Explanation:

During write back police in cache, dirty bit concept is used.
Write back means updates are written only to the cache. When line is modified it’s dirty bit is set and when the line is selected for replacement, the line needs to be written to main memory only if it’s dirty bit is set.

In write back, we first write the cache copy to update the memory. Number of write backs can be reduced if we write only when cache data is different from memory. It is done by dirty bit or modifying bit. It writes back to the cache only when dirty bit is set to 1. Thus, write back cache requires two bits one is valid bit and another is dirty bit.

Diagram:

Data:

Virtual address space (VAS) = 2³² Byte

Physical address space (PAS) = 2²⁸ Byte

Page size (PS) = 2¹¹ Byte

Formula:

\({\rm{number\;of\;pages\;}} = {\rm{P}} = \frac{{{\rm{VAS}}}}{{{\rm{PS}}}}\)

\({\rm{number\;of\;frames}} = {\rm{F}} = \frac{{{\rm{PAS}}}}{{{\rm{PS}}}}\)

Bits required for the virtual page number = ⌈ log₂ P ⌉

Bits required for the physical page number = ⌈ log₂ F⌉

Calculation:

\({\rm{P}} = \frac{{{2^{32}}}}{{{2^{11}}}} = {2^{21}}\)

Bits required for the virtual page number = ⌈ log₂ 2²¹ ⌉ = 21

\({\rm{F}} = \frac{{{2^{28}}}}{{{2^{11}}}} = \;{2^{17}}\)

The correct answer is option 4) 14 and 16

Key Points

• Page size = 1024 bytes → 2¹⁰ bytes, so offset requires 10 bits.
• Total number of pages = 128 → 2⁷, so logical page number requires 7 bits.
• Logical Address = Page Number + Offset → 7 + 10 = 17 bits.
• Physical memory contains 62 page frames → Nearest power of 2 ≥ 62 is 64 → 2⁶ page frames.
• Physical Address = Frame Number + Offset → 6 + 10 = 16 bits.

Additional Information

• Logical Address = bits required to uniquely identify each page (Page number) + Offset within page.
• Physical Address = bits to identify the frame + Offset (same as in logical address).

Hence, the correct answer is: option 4) 14 and 16

The correct answer is me/p.

Key Points

• The page table is a data structure used in computer operating systems to manage the mapping between virtual addresses and physical addresses.
• Each entry in the page table corresponds to a page in the virtual memory and contains information about the physical memory location of that page.
• The size of the page table depends on the number of pages in the process and the size of each page table entry.
• Given:
  • Page size (p)
  • Average process size (m)
  • Size of each page table entry (e)
• To calculate the number of pages, divide the average process size by the page size: m/p
• To find the total space required by the page table, multiply the number of pages by the size of each page table entry: (m/p) * e
• Simplifying the expression gives the total space required as me/p

Additional Information

• The page table allows the operating system to efficiently manage memory allocation and ensure that processes do not interfere with each other's memory.
• Modern operating systems use hierarchical or multi-level page tables to optimize memory usage and reduce the size of page tables for large address spaces.
• Page tables also play a crucial role in implementing virtual memory, allowing systems to use disk space to extend the available physical memory.

The correct answer is Enabling computers to make up for physical memory limitations.

Key Points

• Virtual memory is a memory management capability of an operating system (OS) that uses hardware and software to allow a computer to compensate for physical memory shortages.
• It enables a computer to use more memory than is physically available by temporarily transferring data from random access memory (RAM) to disk storage.
• Virtual memory creates an illusion for users of a very large (main) memory.
• This process is known as "paging" where the OS retrieves data from secondary storage (like a hard drive or SSD) and places it into RAM when needed.
• It allows for the execution of large applications or multiple applications simultaneously without being limited by the actual physical memory installed in the computer.

Additional Information

• Virtual memory helps in multitasking by providing memory space for running multiple programs concurrently.
• It enhances system stability and performance by efficiently managing memory allocation and deallocation.
• Virtual memory can also improve security by isolating different processes, preventing them from interfering with each other.
• The concept of virtual memory was developed in the 1960s to address the limitations of physical memory and to improve the efficiency of computer systems.

Key Points

• Pages are divided into fixed-size slots and hence no external fragmentation. But applications smaller than page size cause internal fragmentation
• Page tables take extra pages in memory. Therefore incur an extra cost

Therefore option 1 and 2 are correct

Memory is word addressable.

1 word = 4 bytes

Virtual Address (VA) = 64 bits

∴ Virtual Address Space (VAS)= 2⁶⁴ words

Physical Address (PA) = 48 bits

∴ Physical Address Space (PAS) = 2⁴⁸ words

Page size (PS) = 8 KB = 2¹¹ words

∴ page offset = 11 bit

∴ number of pages possible = \(\frac{{VAS}}{{PS}} = \frac{{{2^{64}}}}{{{2^{11}}}} = {2^{53}}\)

∴ number of frames possible = \(\frac{{PAS}}{{PS}} = \frac{{{2^{48}}}}{{{2^{11}}}} = {2^{37}}\)

VA = Page number + page offset

Translation Lookaside Buffer (TLB)

Entries in TLB = 128 = 2⁷

If a page number is found in TLB then there will be a hit for all the words (Word addresses) of that Page.

1 - page hit implies 2¹¹ distinct virtual address hits.

So 2⁷page hit implies 2⁷ × 2¹¹=2⁸ × 2¹⁰= 256 × 2¹⁰ virtual address hits.

Therefore, at most 256 × 2¹⁰ distinct virtual addresses can be translated without any TLB miss.

Tips and Tricks:

distinct virtual addresses can be translated without any TLB miss is

the number of entries in TLB × page size

Spooling - It is a process in which data is temporarily held to be used and executed by a device, program or the system

Swapping - It is a memory reclamation method wherein memory contents not currently in use are swapped to a disk to make the memory available for other applications or processes.

Paging - It is a memory management scheme that allows the processes to be stored non-contiguously in the memory.

Relocation - Sometimes, as per the requirements, data is transferred from one location to another. This is called memory relocation.

Data:

TLB hit ratio = p = 90% = 0.9

TLB access time = t = 50 μs

Memory access time = m = 400 μs

Effective memory acess time = EMAT

Formula:

EMAT = p × (t + m) + (1 – p) × (t + m + m)

Calculation:

EMAT = 0.9 × (50 + 400) + (1 – 0.9) × (50 + 400 + 400)

EMAT = 490 μs

∴ the overall access time is 490 μs

Important Points

During TLB hit

Frame number is fetched from the TLB (50 μs)

and page is fetched from physical memory (400 μs)

During TLB miss

TLB no entry matches (50 μs)

Frame number is fetched from the physical memory (400 μs)

Concept:

Paging is a memory management scheme. Paging reduces the external fragmentation. Size of the page table depends upon the number of entries in the table and bytes stored in one entry.

Explanation:

S1: A small page size causes large page tables.

This statement is correct. Smaller page size means more pages required per process. It means large page tables are needed.

S2: internal fragmentation is increased with small pages.

This statement is incorrect. Internal fragmentation means when process size is smaller than the available space. When pages are small, then available space becomes less and there will be less chances of internal fragmentation.

S3: I/O transfers are more efficient with large pages.

An I/O system is required to take an application I/O request and send it to the physical device. Transferring of I/O requests are more efficient with large pages. So, given statement is correct.

The essential content in each entry of a page table is the page frame number.

Explanation:

In paging, physical memory is divided into fixed-size blocks called page frames and logical memory is divided into fixed-size blocks called pages which are of the same size as that of frames. When a process is to be executed, its pages can be loaded into any unallocated frames from the disk.

In paging, mapping of logical addresses to physical addresses is performed at the page level.

• When CPU generates a logical address, it is divided into two parts: page number and offset
• Page size is always in the power of 2.
• Address translation is performed using the page table (mapping table).
• It stores the frame number allocated to each page and the page number is used as an index to the page table.

When the CPU generates a logical address, that address is sent to the MMU (memory management unit). MMU uses the page number to find the corresponding page frame number in the page table. Page frame number if attached to high order end of page offset to form physical address that is sent to the memory.

The mechanism is shown here:

Data:

Virtual address space = 32 bits

Page size = 4 KB = 212 B

number of entries in TLB = number of lines = 128

set associative = 4 -way 

Formula:

number of bits = ⌈log₂ n⌉ 

Number of sets in cache = \(\frac{number\; of\; lines}{set\; associativity}\)

Virtual address = tag + set + page offset (in bits)

Calculation:

set = \(\frac{128}{4} = 2^{5}\)

number of bits in set = 5

32 = tag + 5 + 12

∴ tag = 15 bits

The minimum size of the TLB tag is 15 bits.

Data:

TLB hit ratio = p = 0.8

TLB access time = 15 nanoseconds

Memory access time = m = 150 milliseconds

Formula:

EMAT = p × (t + m) + (1 – p) × (t + m + m)

Calculation:

EMAT = 0.8 × (15 + 150) + (1 – 0.8) × (15 + 150 + 150)

EMAT = 195 nanoseconds.

Important points:

During TLB hit

Frame number is fetched from the TLB (15 ms)

and page is fetched from physical memory (150 ms)

During TLB miss

TLB no entry matches (15 ms)

Frame number is fetched from the physical memory (150 ms)

Data:

TLB hit ratio = 0.8

TLB miss ration = 0.2

TLB reference time = 20 ns

Main Memory reference time = 80 ns

Formula:

Effective memory access time (EMAT)

= TLB hit (TLB time + Main memory time) + TLB miss (TLB time + 2 × Main memory time)

Calculation:

EMAT = 0.8 (20 + 80) + 0.2 (20 + 80 + 80)

= 80 + 36

∴ EMAT= 116 ns

The correct answer is "option 2".

CONCEPT:

Segmentation is a process of dividing each process into variable size segments, where each segment performs related functions.

Segment table stores details about segments. 

Base register of a segment contains the Base address value i.e. smallest physical address from where each segment starts. 

Limit register contains the last range value of a Segment.

CALCULATION:

For a segment address to be in the range of the segment, it must be:

Base address <= segment address <= ( Base address + limit register value)

Since the offset value is exceeding the value of the limit of segment Id2, the trap will be generated.

Hence, the correct answer is "option2".

Additional Information