Combinational Circuits MCQ Quiz - Objective Question with Answer for Combinational Circuits - Download Free PDF

Concept:

The circuit consists of three 2:1 multiplexers. The goal is to realize the function:

F = A + C

Step-by-step Analysis:

1st MUX: Select line = A Inputs = X₀ and X₁ Output = A = A·X₁ + A'·X₀

To get A as output, set: X₀ = 0 (when A=0 → output 0), X₁ = 1 (when A=1 → output 1)

⇒ So, A = A

2nd MUX: Select line = B Inputs = X₂ and X₃ Output = C = B·X₃ + B'·X₂

To get constant output 1 regardless of B, set: X₂ = 1, X₃ = 1

⇒ So, C = 1

3rd MUX: Select line = C Inputs = A and 1 Output = F = C·1 + C'·A = A + C

Final Values:

• X₀ = 0
• X₁ = 1
• X₂ = 1
• X3 = 1

Answer: Option 4) (0, 1, 1, 1)

Sum expression of a half adder is given by:

Sum = A XOR B = \(\bar A\;B + A\;\bar B\)

The implementation of half adder circuit is shown below:

We can conclude that to generate the sum bit, we only need 4 NAND gates.

Explanation:

Given Problem:

The problem requires finding the values of (X₀, X₁, X₂, X₃, X₄, X₅, X₆, X₇) to realize the function F = A + B̅. The correct option is provided as Option 2.

Step-by-Step Solution:

Understanding the Function:

The given function F = A + B̅ is a logical OR operation between A and the complement of B (denoted as B̅).

• In Boolean algebra, the OR operation (denoted by '+') results in a value of 1 if either of the inputs is 1.
• The complement B̅ represents the inverse of B; if B = 0, then B̅ = 1, and if B = 1, then B̅ = 0.

Truth Table:

To realize this function, we construct a truth table for the inputs A and B and the output F:

Mapping Output to (X₀, X₁, ..., X₇):

The values of (X₀, X₁, ..., X₇) correspond to the output F for all possible combinations of 3-bit binary inputs. For inputs A and B, the truth table above gives the first two bits. The third bit (C) is irrelevant for the function F = A + B̅, meaning the output F remains the same regardless of the value of C.

In a 3-bit binary system:

• X₀ corresponds to A = 0, B = 0, C = 0 → F = 1
• X₁ corresponds to A = 0, B = 0, C = 1 → F = 1
• X₂ corresponds to A = 0, B = 1, C = 0 → F = 0
• X₃ corresponds to A = 0, B = 1, C = 1 → F = 0
• X₄ corresponds to A = 1, B = 0, C = 0 → F = 1
• X₅ corresponds to A = 1, B = 0, C = 1 → F = 1
• X₆ corresponds to A = 1, B = 1, C = 0 → F = 1
• X₇ corresponds to A = 1, B = 1, C = 1 → F = 1

Thus, the values of (X₀, X₁, ..., X₇) are (1, 1, 0, 0, 1, 1, 1, 1), which matches Option 2.

Correct Option:

Option 2: (1, 1, 0, 0, 1, 1, 1, 1)

This option correctly represents the output values for the function F = A + B̅ based on the mapping of the truth table.

Important Information

To further understand why other options are incorrect, let’s analyze them:

Option 1: (1, 1, 0, 0, 1, 1, 1, 1)

This option represents the output values for the function F = A + B̅, but it is identical to Option 2. Therefore, it is redundant and not the correct answer.

Option 3: (1, 1, 0, 1, 0, 1, 1, 1)

This option misrepresents the output values of F. For example:

• X₃ (A = 0, B = 1, C = 1) is listed as 1, but based on F = A + B̅, the correct value should be 0.
• X₄ (A = 1, B = 0, C = 0) is listed as 0, but the correct value is 1.

Thus, Option 3 does not match the truth table of F = A + B̅ and is incorrect.

Option 4: (0, 0, 1, 1, 1, 1, 1, 1)

This option completely misrepresents the output values of F. For example:

• X₀ (A = 0, B = 0, C = 0) is listed as 0, but based on F = A + B̅, the correct value should be 1.
• X₂ (A = 0, B = 1, C = 0) is listed as 1, but the correct value is 0.

Thus, Option 4 does not match the truth table of F = A + B̅ and is incorrect.

Conclusion:

Understanding Boolean functions and their truth tables is critical for solving such problems. The correct values of (X₀, X₁, ..., X₇) for the function F = A + B̅ are (1, 1, 0, 0, 1, 1, 1, 1), which matches Option 2. Other options fail to accurately represent the truth table for the given function, leading to incorrect results.

Explanation:

Implementation of a One-Bit Full Adder Using a 3 ∶ 8 Active High Decoder

Definition: A one-bit full adder is a combinational circuit designed to perform the addition of three binary inputs: the two significant bits (A and B) and a carry-in (Cin). It produces two outputs: the sum (S) and carry-out (Cout).

Overview: To implement a one-bit full adder using a 3 ∶ 8 active high output decoder, the decoder is used to generate specific combinations of outputs corresponding to the truth table of the full adder. The outputs of the decoder are then combined using OR gates to derive the required sum and carry outputs.

Working of a 3 ∶ 8 Decoder:

A 3 ∶ 8 decoder takes 3 inputs (A, B, Cin) and generates 8 distinct outputs (Y0 to Y7). Each output corresponds to one unique combination of the inputs. The output is active high, meaning that for a given combination of inputs, only one output is high (logic 1) while the others remain low (logic 0).

For example:

• If A = 0, B = 0, Cin = 0, then output Y0 is high.
• If A = 0, B = 0, Cin = 1, then output Y1 is high.
• If A = 1, B = 1, Cin = 1, then output Y7 is high.

The truth table for a one-bit full adder is as follows:

Implementation:

To implement the full adder using the 3 ∶ 8 decoder, the outputs of the decoder are used to construct the Sum (S) and Carry (Cout) outputs according to the truth table. Each output is obtained by combining specific outputs of the decoder using OR gates.

Deriving Sum (S):

The Sum (S) is high (logic 1) for the following combinations of inputs:

• A = 0, B = 0, Cin = 1 → Decoder output Y1
• A = 0, B = 1, Cin = 0 → Decoder output Y2
• A = 1, B = 0, Cin = 0 → Decoder output Y4
• A = 1, B = 1, Cin = 1 → Decoder output Y7

Thus, Sum (S) = Y1 + Y2 + Y4 + Y7.

Deriving Carry (Cout):

The Carry (Cout) is high (logic 1) for the following combinations of inputs:

• A = 0, B = 1, Cin = 1 → Decoder output Y3
• A = 1, B = 0, Cin = 1 → Decoder output Y5
• A = 1, B = 1, Cin = 0 → Decoder output Y6
• A = 1, B = 1, Cin = 1 → Decoder output Y7

Thus, Carry (Cout) = Y3 + Y5 + Y6 + Y7.

Minimum Number of OR Gates:

To implement the Sum (S) and Carry (Cout) outputs:

• Sum (S) requires four OR gates to combine Y1, Y2, Y4, and Y7.
• Carry (Cout) requires four OR gates to combine Y3, Y5, Y6, and Y7.

However, one OR gate can be shared between Sum (S) and Carry (Cout) for Y7, reducing the total number of OR gates required.

Final Calculation:

Total OR gates = 4 (for Sum) + 4 (for Carry) - 1 (shared gate for Y7) = 7.

Since the question specifies the minimum number of 3-input OR gates, we can combine multiple outputs into groups of three, further reducing the number of gates.

Using this grouping approach:

• Sum (S): Combine Y1, Y2, and Y4 into one 3-input OR gate, and Y7 into another OR gate → 2 OR gates.
• Carry (Cout): Combine Y3, Y5, and Y6 into one 3-input OR gate, and Y7 into another OR gate → 2 OR gates.

Thus, the minimum number of 3-input OR gates required = 4.

Correct Option:

The correct answer is option 3) 4.

Important Information

To analyze the other options:

Option 1 (2 OR gates):

This option is incorrect because it underestimates the number of OR gates required. Each of the Sum (S) and Carry (Cout) outputs requires at least two OR gates to combine the necessary decoder outputs. Therefore, a total of two OR gates is insufficient.

Option 2 (5 OR gates):

This option is incorrect because it does not represent the minimum number of 3-input OR gates required. While 5 OR gates may work, combining outputs into groups of three allows the implementation to be optimized to 4 gates.

Option 4 (3 OR gates):

This option is incorrect because it underestimates the number of OR gates required. Even with optimal grouping, at least 4 OR gates are needed to derive the Sum (S) and Carry (Cout) outputs.

Conclusion:

The minimum number of 3-input OR gates required to implement a one-bit full adder using a 3 ∶ 8 active high decoder is 4, making option 3 the correct choice.

A half adder circuit is made up of an AND gate with an XOR gate as shown below:

• A half adder is also known as XOR gate because XOR is applied to both inputs to produce the sum
• Half adder can add only two bits (A and B) and has nothing to do with the carry
• If the input to a half adder has a carry, then it will neglect it and adds only the A and B bits
• That means the binary addition process is not complete and that's why it is called a half adder

Sum (S) = A⊕B, Carry = A.B

Decoder:

The decoder is a combinational ckt, that convert Binary Coded information into Familiar, representation like the decimal, octal, Hexadecimal, etc.

The decoder has ‘n’ no of i/p & less than equal to 2n O/P

i.e., \(\begin{array}{*{20}{c}} {n \le }&{{2^n}}\\ {\frac{I}{P}}&{\frac{O}{P}} \end{array}\)

For 4 input lines n = 4

Maximum output lines = 2⁴ = 16

Additional Information

Multiplexer (MUX) is defined as:

Based on the select line, it selects the input & produces its output. i.e., at a time one input is taken to get output.

“MUX” is also known as

→ Data selector

→ Parallel to serial converter

→ Many to one circuit.

→ Universal logic Ckt.

Combinational Logic circuits are circuits for which the present output depends only on the present input, i.e. there is no memory element to store the past output.

A combinational circuit can have ‘n’ number of inputs and ‘m’ number of outputs as shown:

Combinational circuits are:

• Multiplexer/Demultiplexer
• Encoder/Decoder
• Adders
• Subtractors
• Code Converters

Multiplexers:

• A multiplexer is Many to one data selector.
• A multiplexer selects one of the many data available at its input depending on the bits on the select line.
• For 2m inputs, there are m select lines that determine which input is to be connected to the output.

In a sequential circuit, the output depends on both the present and the past values. The circuit diagram is as shown:

Examples of sequential circuits:

• Shift Registers
• Flip flops
• Counters

Concept:

In a 4 × 1 MUX

Truth-Table

Y = Output = S̅₁ S̅₀ I₀ + S̅₁ S₀ I₁ + S₁ S̅₀ I₂ + S₁ S₀ I₃

MUX contains AND gate followed by OR gate

Calculation:

By re-drawing circuit diagram

∴ I₀ = 0, I₁ = 1, I₂ = 1, I₃ = 0 & (P = S₁, Q = S₀)

Now output of 4 × 1 MUX is

Y = F = (P̅ Q̅) 0 + (P̅ Q)1 + (P Q̅) 1 + (P Q)0

∴ F = P Q̅ + P̅ Q = P ⊕ Q

∴ F = XOR (P, Q) 

The correct option is 1

Concept:

Multiplexer: It is a device that combines several inputs and outputs them into a single line.

Demultiplexer: It is a device that reverses the process of multiplexer i.e. it converts data from a single input line to multiple output lines.

NAND Gate:

• NAND gate represents the complement of the AND operation.
• The graphic symbol for the NAND gate consists of an AND symbol with a bubble on the output, denoting that a complement operation is performed on the output of the AND gate. 
• The logic NAND function can be expressed by the Boolean expression of, A.B.

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Analysis:

Given A = 1100 and B = 1010

∴ The output will be 0111.

Half adder circuit have two inputs and two outputs (sum and carry).

A half adder circuit is made up of an AND gate with an XOR gate as shown below:

• A half adder is also known as XOR gate because XOR is applied to both inputs to produce the sum
• Half adder can add only two bits (A and B) and has nothing to do with the carry
• If the input to a half adder has a carry, then it will neglect it and adds only the A and B bits
• That means the binary addition process is not complete and that's why it is called a half adder

Sum (S) = A⊕B, Carry = A.B

Combinational Logic circuits are circuits for which the present output depends only on the present input, i.e. there is no memory element to store the past output.

A combinational circuit can have ‘n’ number of inputs and ‘m’ number of outputs as shown:

Combinational circuits are:

• Multiplexer/Demultiplexer
• Encoder/Decoder
• Adders
• Subtractors
• Code Converters

In a sequential circuit, the output depends on both the present and the past values. The circuit diagram is as shown:

Examples of sequential circuits:

• Shift Registers
• Flip flops
• Counters

Concept:

The output of a NOR gate will be at logic 1 when all the input is at logic 0.

• NOR gate is the output (f).
• For the NOR gate whenever there is input(high), It gives Zero.
• The NOR gate is connected with \(D_1,D_4 and D_7\) only, so we have to look after those input only.

Hence, the output of the given circuit is given as:

F = ∑m (0, 2, 3, 5, 6)

Concept: 

For a 2 × 1 MUX is shown above, the output function F is expressed as:

F = S̅₁ I₀ + S₁I₁

i.e. when S₁ = 0, I₀ is transmitted to the output.

And when S₁ = 1, I₁ is transmitted to the output.

Analysis:

The given circuit is redrawn as:

F₁ = S̅₁ w + S₁ w̅

F₁ = S₁ ⊕ w

Now, the required function f will be:

F₂ = F = S̅₂F₁ + S₂F̅₁

F = S₂ ⊕ F₁

F = S₂ ⊕ S₁ ⊕ w

Encoder:

• It is a combinational circuit which converts decimal number into binary number.
• It consists 2ⁿ input lines and n output lines.
• They do not have any select lines.

Additional Information

Decoder:

• It is a combinational circuit which converts binary number into decimal number.
• It consists n input lines and 2ⁿ output lines.
• They also do not have any select lines.

Multiplexer:

• It is a combinational circuit which have many data inputs and single output depending on control or select inputs.​
• For 2^m input lines , m selection lines are required in multiplexer.

De-Multiplexer:

• It is a combinational circuit which have single data input and many data output depending on control or select inputs.​
• For 2^m output lines, m selection lines are required in de-multiplexer.