English
Hindi

Question

Download Solution PDF

Considering equal processing time for each segment, speed-up S achieved by a K-segment instruction pipeline operating on straight sequence of N instructions is given by:

This question was previously asked in
HTET PGT Official Computer Science Paper - 2017
Download PDF Attempt in App
View all HTET Papers >

Answer (Detailed Solution Below)

Option 4 :
Free Tests
View all Free tests >
Free
HTET PGT Official Computer Science Paper - 2019
60 Qs. 60 Marks 60 Mins
Start Now

Detailed Solution

Download Solution PDF

Data:

number of instructions = N

number of stage (segment) = K

Non-pipeline

Assume each stage take 1 unit of time

Time taken (Twp)  = number of stage × number of instructions

Twp  = K.N 

For pipeline 

Only 1st instruction takes K unit time then every (N - 1) instruction takes 1 unit time

Time taken(Tp) = (K + N - 1) 

Therefore option 4 is correct

Download Solution PDF
Latest HTET Updates

Last updated on Jul 12, 2025

-> HTET Exam Date is out. HTET Level 1 and 2 Exam will be conducted on 31st July 2025 and Level 3 on 30 July

-> Candidates with a bachelor's degree and B.Ed. or equivalent qualification can apply for this recruitment.

-> The validity duration of certificates pertaining to passing Haryana TET has been extended for a lifetime.

-> Enhance your exam preparation with the HTET Previous Year Papers.

Exams Tests Super Practice

More Instruction Pipeline Questions

Q1.Which table for a dynamic pipeline become more interesting when a nonlinear pattern is follows?
Q2.A processor chip is used for application in which 30% of execution time is spent on floating point addition. For the new model of the processor, the design team has come up with redesign the floating point adder to make it twice as fast. What will be possible maximum speed up by this redesign? 
Q3.Consider an unpipelined machine with 10nsec clock cycles which uses four cycles for ALU operations and branches where as five cycles for memory operation. Assume that the relative frequencies of these operations are: 40%, 20% and 40%, respectively. Due to clock skew and setup pipeline let us consider that the machine adds one nsec overhead to the clock. How much speedup is observed in the instruction execution rate when a pipelined machine is considered. 
Q4.Direction: The item consists of two statements, one labelled as 'Statement (I)' and the other as 'Statement (II)'. You are to examine these two statements carefully and select the answers to these items using the code given below. Statement (I): Pipeline processing cycle overlaps computer instruction cycle in execution for the  performance improvement. Statement (II): Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub-process being executed in a special dedicated segment that operates concurrently with all other segments.
Q5.Which of the following hazards occurs if the read takes place before the write operation is complete?
Q6.In an instruction execution pipeline, the earliest that the instruction TLB and data TLB can be accessed are 
Q7.Which of the following statements is true?
Q8.Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure. What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?
Q9.On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory. Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address register Decrement the count If count ! = 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design

More Instruction Pipelining Questions

Q1.Consider the following sequence of micro operations : MBR ← PC MAR ← X PC ← Y MEMORY ← MBR Which one of the following is possible operation performed by this sequence ?
Q2.Correct the order of instruction cycle: A. Read the effective address B. Fetch the information C. Execute the instruction D. Decode the instruction Choose the correct answer from the options given below:
Q3.Consider a pipeline unit for fixed - point multiplication of 8-bit integers. Arrange the following stages in a correct sequence. Stage A : Consists of two CSAS and it merges four numbers from previous stage. Stage B : is a CPA, which adds up the two numbers Stage C : is made upto two level of four CSAS. Stage D : Generates eight partial products. Choose the correct answer from the options given below:
Q4.Which table for a dynamic pipeline become more interesting when a nonlinear pattern is follows?
Q5.A system bus in which each data item is transferred during a time slice known in advance to both units source and destination is called:
Q6.In most general case, the computer needs to process each instruction with the following sequence of steps: (A) Calculate the effective address (B) Execute the instruction (C) Fetch the instruction from memory (D) Fetch the operand from memory (E) Decode the instruction Choose the correct answer from the options given below:
Q7.A processor chip is used for application in which 30% of execution time is spent on floating point addition. For the new model of the processor, the design team has come up with redesign the floating point adder to make it twice as fast. What will be possible maximum speed up by this redesign? 
Q8.The correct sequence in fetch-execute cycle is ______ A. Decode B. Fetch C. Execute Chose the correct answer from the following 
Q9.Consider an unpipelined machine with 10nsec clock cycles which uses four cycles for ALU operations and branches where as five cycles for memory operation. Assume that the relative frequencies of these operations are: 40%, 20% and 40%, respectively. Due to clock skew and setup pipeline let us consider that the machine adds one nsec overhead to the clock. How much speedup is observed in the instruction execution rate when a pipelined machine is considered. 
Q10.Direction: The item consists of two statements, one labelled as 'Statement (I)' and the other as 'Statement (II)'. You are to examine these two statements carefully and select the answers to these items using the code given below. Statement (I): Pipeline processing cycle overlaps computer instruction cycle in execution for the  performance improvement. Statement (II): Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub-process being executed in a special dedicated segment that operates concurrently with all other segments.
Suggested Test Series
View All >
Social Science (SST) Content for All Teaching Exams - Let's Crack TET!
191 Total Tests with 1 Free Tests
Start Free Test
HTET TGT Level 2 - 2024 Mock Test
183 Total Tests with   3 Free Tests
Start Free Test

NIC Scientist B Important Links

VacancyExam DateEligibilitySelection ProcessAdmit CardSyllabus

More Computer Organization and Architecture Questions

Q1.Which of the following statement(s) is/are correct? Statement A : ALU can perform both arithmetic and logical operations. Statement B : CPU is used to process, display and store data or information.
Q2.The addressing mode/s, which uses the PC instead of a general-purpose register is : 
Q3.A microprogrammed control unit : 
Q4.Consider the following sequence of micro operations : MBR ← PC MAR ← X PC ← Y MEMORY ← MBR Which one of the following is possible operation performed by this sequence ?
Q5.In the case of, Zero-address instruction method the operands are stored in __________.
Q6.A demultiplexer is used to :
Q7.More than one word is put in one cache block to : 
Q8.Which method bypasses the CPU for certain types of data transfer operation ?
Q9.If the virtual memory size is 32 MB and a physical memory size is 4MB with a page size of 2KB, Calculate the number of frames available in physical memory
Q10.Which of the following is the correct sequence with regard to service routine? A. Save contents of processor registers B. Turn the interrupt facility on C. Service the device whose flag is set D. Check which flag is set E. Restore contents of processor registers Choose the correct answer from the options given below:
Testbook Edu Solutions Pvt. Ltd.
1st & 2nd Floor, Zion Building,
Plot No. 273, Sector 10, Kharghar,
Navi Mumbai - 410210
support@testbook.com
Toll Free:1800 833 0800
Office Hours: 10 AM to 7 PM (all 7 days)
Company
About usCareers We are hiringTeach Online on TestbookPartnersMediaSitemap
Products
Test SeriesTestbook PassOnline CoursesOnline VideosPracticeBlogRefer & EarnBooks
Copyright © 2014-2022 Testbook Edu Solutions Pvt. Ltd.: All rights reserved
User PolicyTermsPrivacy
Hot Links： real teen patti teen patti glory teen patti gold new version teen patti master 2025 all teen patti game