D Flip-Flop MCQ Quiz in தமிழ் - Objective Question with Answer for D Flip-Flop - இலவச PDF ஐப் பதிவிறக்கவும்
Last updated on Apr 18, 2025
Latest D Flip-Flop MCQ Objective Questions
Top D Flip-Flop MCQ Objective Questions
D Flip-Flop Question 1:
In JK Flip flop, if we input K with the inverted from of what we input J, the resultant flip flop is
Answer (Detailed Solution Below)
D Flip-Flop Question 1 Detailed Solution
The given is drawn as:
This is a standard D flip flop circuit.
Analysis:
Step-1:
The characteristic table of the required flipflop i.e D flipflop is:
|
D |
Q |
Qn+1 |
|
0 |
0 |
0 |
|
0 |
1 |
0 |
|
1 |
0 |
1 |
|
1 |
1 |
1 |
Step-2:
The excitation table of the given flip-flop i.e. Jk flipflop is:
|
Q |
Qn+1 |
J |
K |
|
0 |
0 |
0 |
X |
|
0 |
1 |
X |
1 |
|
1 |
0 |
1 |
X |
|
1 |
1 |
X |
0 |
Step-3:
The K-map for both J and K individually will be:
Step-4:
Now make the connections accordingly to get:
Note: This is a standard flipflop conversion. of making a D flipflop from JK flipflop.
D Flip-Flop Question 2:
Consider the circuit given below with initial state Q0 = Q1 = Q2 = 0. The state of the circuit is given by the value 4Q2 + 2Q1 + Q0.
Which is the correct state sequence not possible from the above given circuit?
Answer (Detailed Solution Below)
D Flip-Flop Question 2 Detailed Solution
|
Q2 |
Q1 |
Q0 |
D2 |
D1 |
D0 |
Q2N |
Q1N |
Q0N |
|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
|
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
|
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
|
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
|
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
D Flip-Flop Question 3:
Which of the following is true about the behaviour of a D Flip-Flop when the clock input is NOT transitioning?
Answer (Detailed Solution Below)
D Flip-Flop Question 3 Detailed Solution
The correct statement about the behavior of a D Flip-Flop when the clock input is NOT transitioning is: 1) The output remains at the last value.
Explanation:
-
Edge-Triggered Behavior: A D flip-flop is an edge-triggered device. This means it samples its input (D) and updates its output (Q) only at a specific transition of the clock signal (either the rising edge or the falling edge, depending on its design).
-
Latched State: When the clock input is not transitioning (i.e., it's held high, held low, or in between edges), the flip-flop is in a latched state. In this state, its output is isolated from the D input. Any changes in the D input during this period will not affect the output. The output simply holds the data that was present at the last active clock edge.
D Flip-Flop Question 4:
Consider the following circuit
The flip-flops are positive edge triggered D FFs
If Initially Q1Q0 = 00 then what is the state transition sequence?
Answer (Detailed Solution Below)
D Flip-Flop Question 4 Detailed Solution
|
Q1 |
Q0 |
D1 |
D0 |
Q1N |
Q0N |
|
0 |
0 |
1 |
1 |
1 |
1 |
|
0 |
1 |
0 |
0 |
0 |
0 |
|
1 |
0 |
0 |
1 |
0 |
1 |
|
1 |
1 |
1 |
0 |
1 |
0 |
D Flip-Flop Question 5:
The state transition diagram of the logic circuit shown below is –
Answer (Detailed Solution Below)
D Flip-Flop Question 5 Detailed Solution
When
In the flip-flop
D Flip-Flop Question 6:
The characteristic equation of following Flip – Flop is
Answer (Detailed Solution Below)
D Flip-Flop Question 6 Detailed Solution
Characteristic equation of normal JK FF is
D Flip-Flop Question 7:
Which of the following are true
Answer (Detailed Solution Below)
only 2
D Flip-Flop Question 7 Detailed Solution
In S, R flip flop
S = 1, R = 1 in valid states
So only 2 is true
D Flip-Flop Question 8:
Comprehension:
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
Answer (Detailed Solution Below)
011
D Flip-Flop Question 8 Detailed Solution
From the table shown in the explanation of above question, if first state is 010 next State is 011.
D Flip-Flop Question 9:
Comprehension:
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.
If all the flip-flops were reset to 0 at power on, what is the total number of Distinct outputs (states) represented by PQR generated by the counter?
Answer (Detailed Solution Below)
4
D Flip-Flop Question 9 Detailed Solution
|
CLOCK |
Inputs |
Outputs |
||||
|
|
D1 = R |
\(D_2= \overline {(P+R)} \) |
\(D_3=Q\overline{R }\) |
P |
Q |
R |
|
1 |
0 |
1 |
0 |
0 |
1 |
0 |
|
2 |
0 |
1 |
1 |
0 |
1 |
1 |
|
3 |
1 |
0 |
0 |
1 |
0 |
0 |
|
4 |
0 |
0 |
0 |
0 |
0 |
0 |